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Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GL120 /SDIO /CAPAB2

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Interpret as CAPAB2

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https://regviz.com/r/Silicon Labs/Series1/EFM32GG11B/EFM32GG11B420F2048GL120/SDIO/CAPAB2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDR50SUP)SDR50SUP 0 (SDR104SUP)SDR104SUP 0 (DDR50SUP)DDR50SUP 0 (DRVTYPASUP)DRVTYPASUP 0 (DRVTYPCSUP)DRVTYPCSUP 0 (DRVTYPDSUP)DRVTYPDSUP 0TIMCNTRETUN 0 (USETUNSDR50)USETUNSDR50 0RETUNEMODES 0CLOCKKMUL0 (SPIMODE)SPIMODE 0 (SPIBLOCKMODE)SPIBLOCKMODE

Description

Capabilities Register to Hold Bits 63~32

Fields

SDR50SUP

SDR50 Support
SDR104SUP

SDR104 Support
DDR50SUP

DDR50 Support
DRVTYPASUP

Driver Type a Support
DRVTYPCSUP

Driver Type C Support
DRVTYPDSUP

Driver Type D Support
TIMCNTRETUN

Timer Count for Re-Tuning
USETUNSDR50

Use Tuning for SDR50
RETUNEMODES

Re-tuning Modes
CLOCKKMUL

Clock Multiplier
SPIMODE

SPI Mode Support
SPIBLOCKMODE

SPI Block Mode Support

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data